1. Field of the Invention
The present invention relates to a method for error control in multilevel memory cells with a configurable number of stored bits.
2. Description of the Related Art
As is known, thanks to the evolution of technological processes, which makes it possible to provide elementary devices of ever smaller size, in the last few years semiconductor memories have been produced that have very high storage capacities.
A further increase in the storage capacity has be obtained by resorting to multilevel storage, which enables the storage density to be increased, given the same technological generation. In fact, with the above technique it is possible to store more than one data bit within the individual memory cell normally used to contain a single bit.
It is moreover known that, in order to read a two-level memory cell (containing 1 bit), an appropriate electrical quantity, correlated to the status of the cell, is compared with a reference value, and according to the outcome of the comparison it is determined whether the memory cell contains a logic “0” or a logic “1”.
In the case of cells that can contain r bits, reading is carried out by comparing the electrical quantity correlated to the status of the memory cell with 2r−1 reference levels. The outcome of the comparisons makes it possible to determine in which of the 2r intervals allowed the memory cell is found, and then to reconstruct the contents of the memory cell in terms of binary data.
The multilevel approach can be applied both to volatile memories (such as DRAMs) and to nonvolatile memories (such as EEPROM and Flash memories). In any case, the increase in the number of bits per cell renders tolerance to disturbance, retention of data, and accuracy of reading and writing operations more critical. In addition, the increase in the storage capacity demanded by the market tends to reduce the overall reliability. For these reasons, it is to be expected that the use of error-control codes will be of fundamental importance, above all in the case of high-capacity multilevel memories.
At present, the devices with the highest capacity present on the market store some hundred million bits, and the forecast for the next few years is for devices having increasingly higher capacities.
The increase in the number of cells tends to reduce the mean time to failure (MTTF) of the entire memory device. However, given the need to create increasingly more reliable equipment or systems, the level of reliability required for the individual memory component becomes increasingly more stringent. For this reason, dedicated design techniques are adopted, as well as a quality control on the production processes, in order to prevent or reduce failures.
However, malfunctionings of memory chips cannot be eliminated completely and can be reduced only at the expense of a reduction in performance or an increase in costs.
A very effective way for increasing reliability consists in designing error-immune memories using error-control codes, i.e., codes that are able to detect and correct errors in the data stored in the memories.
In particular, codes for the correction of a single error or for detection of a double error and correction of a single error are used in semiconductor memory devices of various types.
In particular, errors in memories are normally classified as “soft” errors and “hard” errors. By “soft” error is meant a random, non-repetitive. and non-permanent change in the status of a cell. Soft errors are caused by an occasional electrical noise or are induced by radiation (a particles, cosmic rays, etc.), regard a very limited number of cells each time, and can be recovered in the next writing cycle.
By “hard” error is instead meant a permanent physical failure associated to defects present in the device or arising during its operation on account of the incapacity of the materials to withstand the stresses applied. Generally speaking, hard errors are much rarer than soft errors.
Error-control codes enable a drastic reduction of the effects of soft errors, which represent the more serious problem, especially for multilevel memories. However, they may prove useful also for recovering some hard errors.
In order to protect the data that is to be stored in a memory, it is necessary to add, to the bits forming each data word, a certain number of control or parity bits, appropriately calculated. The operation that associates to each data word a precise value of the control bits is referred to as encoding. The control bits calculated by the circuit that carries out encoding must be stored together with the data word.
Each word stored will be subsequently read together with the control bits that belong to it. The decoding circuit is able to detect and correct a certain number of erroneous bits per word by appropriately comparing the value of the control bits with the value of the data bits.
The number of control bits that it is necessary to add to each data word is determined according to the length of the data word itself and to the number of errors per word that it is desired to correct.
More in general, error-control encoding may be extended from the binary alphabet (which contains only the two symbols “0” and “1”) to a larger alphabet containing q symbols. In the latter case, encoding consists in adding a certain number of symbols (no longer bits) to each word to be stored, and the correction of the errors consists in correcting the erroneous symbols.
The aforesaid extension to the q-ary case is particularly suited to multilevel memories, in which each memory cell is able to store more than one bit (for instance, r bits). In this case, in fact, malfunctioning of a memory cell may degrade the values of all the bits stored therein. It is therefore more convenient to associate, to each block of r bits stored in a single cell, a q-ary symbol, i.e., a symbol belonging to an alphabet formed by q=2r distinct symbols. Each symbol is then stored in a distinct multilevel memory cell. In this way, each k-bit data word is viewed as a word formed by k/r q-ary symbols (corresponding to the number of memory cells that form each word), and correction of a symbol is equivalent to the correction of all the r bits associated thereto.
The error-control methods integrated in a semiconductor memory must meet three fundamental requirements:                the time required for the encoding operation and for the decoding operation (which comprises error detection and correction) must affect the memory access time only to a minimal extent;        the additional area due to the encoding and decoding circuit and to the control cells must be minimized; and        the technique used must at least guarantee correction of any type of error on the individual cell, which, in the case of multilevel cells, may mean the error on a number of bits.        
To prevent the times for encoding and decoding from degrading the access time, recourse may be typically had to the use of parallel-encoding structure or matrix-encoding structures, which enable the highest calculation speeds.
As regards, instead, the second requirement, the area is minimized by choosing codes with characteristics suitable for the particular application and appropriately optimized.
Finally, the last requirement is guaranteed by the use of q-ary codes, which enable detection and correction of errors on memory cells, irrespective of the number of erroneous bits associated to each of said cells.
Multilevel memories designed to store r bits per cell may, however, also operate with storage of a smaller number of bits per cell. In this case, for reading and writing it is possible to use a subset of the 2r−1 reference levels available. The extreme and simplest example of this operating condition is represented by the case in which a multilevel memory is used as a normal two-level memory.
The choice of reducing the number of bits stored in each cell reduces the storage capacity of the memory but increases its reliability. For example, in the case of nonvolatile memories, the reduction in the number of bits stored in each cell makes it possible to guarantee retention of the data for a longer time and in more unfavorable environmental conditions.
Normally, the choice of the operating mode is made in a permanent way by the producer. In particular, the choice of the operating mode may be advantageous for obtaining a memory with a smaller number of bits per cell as a sub-selection of a memory designed for storing a higher number of bits, in order to achieve an overall reduction in costs, or else this operating mode may be adopted either because there exists the need to obtain, from the same memory device, different sizes of memory, or else, more simply, for reasons of debugging of the memory device. In fact, when a first prototype of a new memory device is manufactured on silicon, it may be useful to have the possibility of switching to operating modes that are simpler than the normal ones in order to enable verification of the operation of the circuitry in circumstances that are less critical than the nominal ones.
Currently, moreover, in order to meet the growing demand of the market, memory devices are being designed in which also the end user can decide on the operating mode according to the type of use of the device, and consequently the need is increasingly felt of adopting a polyvalent error-control code that is able, using the same circuits, to protect the data stored in cells that operate at a different number of levels.
The aforesaid need is further strengthened by the fact that the memory devices of the next generations, with large storage capacities, will be able to be configured sector by sector and will thus have internal sectors set with a different number of bits (see, for example, the U.S. Pat. No. 5,574,879). It will be possible to use memory devices of this type, for instance, inside multimedia cards, so enabling storage, in sectors with a low number of bits per cell, of the microcode for the microprocessor that manages the card, and storage, in sectors with a high number of bits per cell, of the user data.
However, the error-control codes currently used in Flash memories are block codes implemented with CMOS logic networks, and their functionality is fixed once and for all in the design phase of the memory device. In fact, in the definition of this type of codes, the designer fixes once and for all some structural characteristics of the code which fix the limits of use thereof to the specific sphere for which the code is designed. In particular, during the code-design phase the choices are made as regards the number of bits on which the code is to operate, the error-correction capacity of the code, and the alphabet and the number of symbols of the alphabet with which to operate.
The number of parity bits required depends upon the above choices, and consequently it is evident that error-control codes that operate effectively in memory devices storing a given number of bits per cell are different from error-control codes designed to operate in memory devices storing a smaller number of bits per cell.